Call for Papers

The "power wall" has forced chip and system architects to design with smaller margins between nominal and worst-case operating points. Dynamic power, voltage noise and thermal management control loops have already become an integral part of chip and system design. New research papers in “wear out” and general reliability management have recently been published. These new generation management protocols have, however, opened up other sources of concern: e.g. control loop stability and robustness of the management protocols. The potential security holes exposed by the integrated control loops and system safety issues triggered by potential violations of power or thermal limits are other areas of concern. Also, side channel attack scenarios enabled by modulated power profiles have been documented in prior research. We seek to motivate the research community into adopting a holistic approach to mitigating the power wall and the concomitant reliability-security wall. We have coined the term "Energy-Secure System Architectures" to cover the range of research being pursued within industry and academia in order to ensure robust and secure functionality, while meeting the energy-related constraints of the "green computing" era. This segmented workshop offering, composed of lectures provided by experts in the areas of power/thermal management, reliability and security, provides a comprehensive view of the hardware and software aspects of Energy-Secure System Architectures. Authors are invited to submit an extended abstract (2 pages in length) on the workshop theme, focusing on the interactions of power management and security. Topics of interest include (but are not limited to):

  • Power, noise and thermal management solutions for modern multi-core platforms: with a focus on reliability and security challenges.
  • Verification and design for verification of system-level power, noise and thermal managers: predeployment safeguards against security breaches.
  • Reliability and security holes exposed by power/thermal management protocols: specific examples of attack scenarios.
  • Security-aware dynamic power management: software-hardware architectural concepts.
  • Use of machine learning/deep learning (ML/DL) principles in safeguarding against energy attacks in processors, server systems and data-centers.
  • Architectural implications of and system software support for energy-secure systems.
  • Security and reliability issues in emerging low power processor and memory technology.
  • Resilience and security challenges of ultra-low power cognitive IoT systems
  • Energy-secure artificial intelligence (AI) systems.
  • Metrics for quantifying energy-security of computing systems.

Accepted papers will be presented at the workshop and included in the workshop report. Selected papers presented in the workshop will be invited to submit revised (updated) versions to a peer-reviewed special issue of IEEE Security and Privacy (to be organized; co-guest edited by the organizers of this workshop).

Extended abstracts must be in English of up to 2 pages. To submit extended abstracts to the workshop, click here. If you have questions regarding submission, please contact us:,

Important Dates

  • Submission deadline: March 1st, 2019
  • Acceptance decision: March 15th, 2019
  • Final submission: April 5th, 2019
  • Presentation Slides: April 26th, 2019

Organizing Committee

  • Saibal Mukhopadhyay, Georgia Tech University — coChair
  • Pradip Bose, IBM T.J.Watson Research Center— coChair

Technical Program Committee

  • Saibal Mukhopadhyay, Georgia Tech University
  • Pradip Bose, IBM Research
  • Alper Buyuktosunoglu, IBM Research
  • Augusto Vega, IBM Research
  • Francisco J. Cazorla, Barcelona Supercomputing Center
  • Simha Sethumadhavan, Columbia University
  • Moinuddin Qureshi, Georgia Tech University
  • Edward Suh, Cornell University
  • Sanu Matthew, Intel Corporation

Web/Publicity Chair

  • David Trilla, UPC and Barcelona Supercomputing Center

Submission Deadline
March 1st, 2019

Acceptance Decision
March 15th, 2019

Final Submission
April 5th, 2019

Presentation Slides
April 26th, 2019



Thursday May 9th, 2019
11:00 - 12:00 ESSA Registration (for HOST attendees and ESSA-only attendees)
13:15 - 13:30 Introduction and Welcoming Remarks
13:30 - 14:15 KEYNOTE 1: from Government
14:15 - 15:00 KEYNOTE 2: from Industry
15:00 - 15:30 BREAK
15:30 - 18:00 Technical Paper Session 1 (2 hour 30 minutes) [6x25]
18:00 - 21:00 Reception/Social Event (with Student Poster); joint with TAME workshop
Friday May 10th, 2019
07:00 - 08:00 Continental Breakfast [joint with TAME]
08:00 - 9:15 Panel Discussions
09:15 - 9:45 BREAK
09:45 - 11:45 Technical Paper Session 2 (2 hour 30 minutes) [6x25]
11:45 - 12:00 Closing Remarks


Saibal Mukhopadhyay is a Professor at Georgia Tech University. His interests focus on VLSI Systems and Digital Design, Electronic Design and Applications and Nanotechnology. He also worked at IBM T. J. Watson Research Center as research staff member where his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. Dr. Mukhopadhyay has (co)-authored over 250 papers in reputed conferences and journals and filed four United States patents. He is a Fellow of the IEEE.

Pradip Bose is a Distinguished Research Staff Member and manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over thirty-three years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D. degree from University of Illinois at Urbana-Champaign.


ESSA will be held in conjunction with the 12th IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2019). Refer to the main venue to continue with the registration process.

Event Location

The Hilton
7920 Jones Branch Drive
McLean, VA 22102

Check main venue site for more information.